Semiconductor fabrication that includes surface tension control

ABSTRACT

In one embodiment, a method includes providing a semiconductor substrate that includes a memory container having a double-sided capacitor. The method also includes vapor phase etching a layer adjacent to the side wall of the memory container with a vapor having a surface tension lowering agent.

This application is a Divisional of U.S. application Ser. No.10/789,800, filed Feb. 27, 2004, which is incorporated herein byreference.

FIELD OF THE INVENTION

The present invention relates generally to the field of semiconductorfabrication, and more particularly to semiconductor fabrication thatincludes surface tension control.

BACKGROUND

Semiconductors are used extensively in today's electronic devices. Theirminiature size and low power requirements enable highly complex circuitsto be used in places never before thought possible. This has led to thedevelopment of systems with the speed and power to make our lives easierwithout encumbering us with bulky boxes and power-hungry electronics.One of the keys to both light weight and energy efficiency is the tinysize of the circuitry. With each new generation of circuit technology,comes smaller and smaller device sizes.

Many electronic systems include a memory device, such as a DynamicRandom Access Memory (DRAM), to store data. A typical DRAM includes anarray of memory cells. Each memory cell includes a capacitor that storesthe data in the cell and a transistor that controls access to the data.The capacitor includes two conductive plates. The top plate of eachcapacitor is typically shared, or common, with each of the othercapacitors. This plate is referred to as the “top cell plate.” Thecharge stored across the capacitor is representative of a data bit andcan be either a high voltage or a low voltage. Data can be either storedin the memory cells during a write mode, or data may be retrieved fromthe memory cells during a read mode. The data is transmitted on signallines, referred to as digit lines, which are coupled to input/output(I/O) lines through transistors used as switching devices. Typically,for each bit of data stored, its true logic state is available on an I/Oline and its complementary logic state is available on an I/O complementline. Thus, each such memory cell has two digit lines, digit and digitcomplement.

Typically, the memory cells are arranged in an array and each cell hasan address identifying its location in the array. The array includes aconfiguration of intersecting conductive lines, and memory cells areassociated with the intersections of the lines. In order to read from orwrite to a cell, the particular cell in question must be selected, oraddressed. The address for the selected cell is represented by inputsignals to a word line decoder and to a digit line decoder. The wordline decoder activates a word line in response to the word line address.The selected word line activates the access transistors for each of thememory cells in communication with the selected word line. The digitline decoder selects a digit line pair in response to the digit lineaddress. For a read operation, the selected word line activates theaccess transistors for a given word line address, and data is latched tothe digit line pairs.

Some circuit devices utilize “container” structures, and such containerstructures are often utilized as a capacitor for a memory cell due totheir efficient use of semiconductor die real estate. After formation,these container structures look like tiny holes within the surroundingmaterial. They will generally have a closed bottom, an open top and sidewalls extending between the closed bottom and open top. Typically,containers that will be formed into capacitor structures will havedimensions that are taller than they are wide, often referred to as a“high aspect-ratio.” This high aspect-ratio of container capacitors canallow the capacitor to store more energy while maintaining the sametwo-dimensional surface area.

However, capillary forces may cause the container structures of thememory array to lean and/or stick together. In particular, because ofthe proximity of these container structures, surface tension (caused bythe capillary forces) caused by liquids used for the removal of certainmaterials (e.g., an oxide) during fabrication may cause the containerstructures to be pulled together. For example, the liquid used during awet etch operation to remove an oxide may introduce such capillaryforces into the fabrication of the memory array.

Thicker absorbed layers etch the underlying layer more quickly as a costof having more surface tension. Therefore, a typical approach to reducesurface tension is to maintain a very thin layer of absorbed material onthe surface of the layer being etched. Accordingly, such an approachrequires more vapor etching tools to decrease the time to perform vaporetch operations. In other words, more vapor etching tools are added tooperate in parallel. This can be prohibitive in terms of cost and thefootprint (space) needed to accommodate such tools.

For the reasons stated above, for other reasons stated below, and forother reasons which will become apparent to those skilled in the artupon reading and understanding the present specification, there is aneed in the art an improved methods, apparatuses and systems forsemiconductor fabrication.

SUMMARY

Methods, apparatuses and systems for semiconductor fabrication thatincludes surface tension control are described. In one embodiment, amethod includes providing a semiconductor substrate that includes amemory container having a double-sided capacitor. The method alsoincludes vapor phase etching a layer adjacent to the side wall of thememory container with a vapor having a surface tension lowering agent.

In one embodiment, there is a method of fabricating a semiconductorsubstrate. The method includes placing a semiconductor substrate thatincludes a double-sided capacitor container in a chamber. The methodalso includes vapor phase etching a layer adjacent to a side wall of thedouble-sided capacitor container with a vapor that includes hydrogenfluouride, an etch initiator composition and an alcohol.

In an embodiment, there is a method of fabricating an integratedcircuit. The method includes housing the integrated circuit in a vaporetch chamber. The method also includes vapor phase etching an insulatorlayer formed adjacent to a double-sided capacitor container in theintegrated circuit. The vapor phase etching of the oxide layer comprisesinserting a vapor comprised of a hydrogen fluoride and isopropyl alcoholinto the vapor etch chamber.

In one embodiment, a method includes placing a substrate that includesan array of memory into a chamber. The array of memory has at least onememory container with a side wall with an embedded capacitor. The methodalso includes vapor phase etching of a layer of an insulator materialformed adjacent to the side wall. The vapor phase etching comprisesmixing a hydrogen fluoride and an isopropyl alcohol to form a mixedvapor. The vapor phase etching also includes inserting the mixed vaporinto the chamber.

In an embodiment, there is a method for fabricating a semiconductorsubstrate. The method includes placing the semiconductor substrate thatincludes a memory container into a vapor etching chamber. A side wall ofthe memory container includes a double-sided capacitor. The method alsoincludes vapor phase etching of a layer of an insulator material formedadjacent to the side wall of the memory container. The vapor phaseetching includes mixing an the etch initiator composition, hydrogenfluoride and alcohol to form a mixed vapor. The vapor phase etching alsoincludes heating the mixed vapor. The vapor phase etching includesinserting the mixed vapor into the vapor etching chamber.

In one embodiment, a method includes placing a semiconductor substrateinto a chamber. The method also includes vapor phase etching of aninsulator material formed adjacent to a double-sided container on asemiconductor substrate. The vapor phase etching comprises forming avapor that includes an etch initiator composition, an HF gas and asurface tension lowering agent. The vapor phase etching also includesinserting the vapor into the chamber.

In an embodiment, there is a method for fabricating a memory array. Themethod includes forming at least one memory container in aborophosphosilicate glass (BPSG) material on a substrate. A side wall ofthe at least one memory container includes a double-sided capacitor. Themethod also includes removing at least a part of the BPSG material basedon a vapor wet etch operation with a vapor comprised of hydrogenfluoride and alcohol.

In one embodiment, a method includes forming at least one memorycontainer in an oxide, wherein a side wall of the at least one memorycontainer includes a double-sided capacitor. The method also includesvapor wet etching of a layer of the oxide with a vapor comprised ofhydrogen fluoride, H₂O and a surface tension lowering agent.

In an embodiment, a vapor phase etching system includes an etchinitiator composition source, a hydrogen fluoride source and a surfacetension lowering agent source. The vapor phase etching system alsoincludes a heater to receive an etch initiator composition from the etchinitiator composition source, hydrogen fluoride from the hydrogenfluoride source and a surface tension lowering agent from the surfacetension lowering agent source. The heater heats the etch initiatorcomposition, the hydrogen fluoride and the surface tension loweringagent to form a mixed vapor. The vapor phase etching system alsoincludes a chamber to house a semiconductor substrate that includes atleast one memory container. A side wall of the at least one memorycontainer includes a double-sided capacitor that is adjacent to aninsulator layer. The mixed vapor is to be inserted into the chamber.

In one embodiment, a system includes a processor to execute a number ofinstructions. The system also includes a memory to store at least a partof the number of instructions. The memory has a number of memory cells,wherein the number of memory cells includes a double-sided capacitorfabricated in a side wall of a memory container. The number of memorycells are fabricated by forming the memory container in an oxide. Thenumber of memory cells are also fabricated by vapor wet etching of alayer of the oxide with a vapor comprised of a hydrogen fluoride, anetch initiator composition and a surface tension lowering agent.

In an embodiment, an integrated circuit device comprises a first memorycontainer having a side wall that includes a double-sided capacitor. Theintegrated circuit device includes a second memory container having aside wall that includes a double-sided capacitor. The first memorycontainer and the second memory container are formed by vapor phaseetching, with a vapor, an oxide layer between the side wall of the firstmemory container and the side wall of the second memory container. Thevapor includes a surface tension lowering agent.

In one embodiment, a memory device comprises an array of memory cellsformed within a number of memory containers. A side wall of at least oneof the number of memory containers has a double-sided capacitor. The atleast one of the number of memory containers is formed by vapor phaseetching a layer adjacent to the side wall with a vapor that includes asurface tension lowering agent.

In an embodiment, an integrated circuit comprises a substrate. Theintegrated circuit includes a memory container formed on the substrateby forming the memory container in a borophosphosilicate glass (BPSG)material on the substrate, wherein a side wall of the memory containerincludes a double-sided capacitor. The memory container is also formedon the substrate by removing at least a part of the BPSG material basedon a vapor wet etch operation with a vapor comprised of a hydrogenfluoride gas and an alcohol.

In one embodiment, an array of memory cells comprises a substrate. Thearray of memory cells also includes a structure having a side wall thatincludes a double-sided capacitor. The structure is formed on thesubstrate by vapor phase etching a layer adjacent to the side wall witha vapor that includes methanol.

In an embodiment, a memory includes a substrate. The memory includes anumber of memory containers having side walls that includes adouble-sided capacitor. The number of memory containers are formed onthe substrate by etching an insulator layer adjacent to the side wallswith a vapor that includes a hydrogen fluoride gas, an H₂O vapor and asurface tension lowering agent.

These and other embodiments, aspects, advantages, and features of thepresent invention will be set forth in part in the description whichfollows, and in part will become apparent to those skilled in the art byreference to the following description of the invention and referenceddrawings or by practice of the invention. The aspects, advantages, andfeatures of the invention are realized and attained by means of theinstrumentalities, procedures, and combinations particularly pointed outin the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention may be best understood by referring to thefollowing description and accompanying drawings which illustrate suchembodiments. The numbering scheme for the Figures included herein aresuch that the leading number for a given reference number in a Figure isassociated with the number of the Figure. For example, a memory array100 can be located in FIG. 1. However, reference numbers are the samefor those elements that are the same across different Figures. In thedrawings:

FIG. 1 illustrates a system for semiconductor fabrication that includessurface tension control, according to one embodiment of the invention.

FIG. 2 illustrates a semiconductor substrate, according to oneembodiment of the invention.

FIG. 3 illustrates a fabrication of the semiconductor substrate of FIG.2 at a first stage, according to one embodiment of the invention.

FIG. 4 illustrates a fabrication of the semiconductor substrate of FIG.2 at a second stage, according to one embodiment of the invention.

FIG. 5 is a simplified block diagram of a memory device, according toone embodiment of the invention.

FIG. 6 illustrates a semiconductor die, according to one embodiment ofthe invention.

FIG. 7 illustrates a circuit module, according to one embodiment of theinvention.

FIG. 8 illustrates a circuit module as a memory module, according to oneembodiment of the invention.

FIG. 9 illustrates a block diagram of an electronic system, according toone embodiment of the invention.

FIG. 10 illustrates a block diagram of an electronic system as a memorysystem, according to one embodiment of the invention.

FIG. 11 illustrates a block diagram of an electronic system as acomputer system, according to one embodiment of the invention.

DETAILED DESCRIPTION

Methods, apparatuses and systems for different embodiments forsemiconductor fabrication that includes surface tension control aredescribed. In the following detailed description of the embodiments,reference is made to the accompanying drawings which form a part hereof,and in which is shown by way of illustration specific embodiments inwhich the inventions may be practiced. These embodiments are describedin sufficient detail to enable those skilled in the art to practice theinvention, and it is to be understood that other embodiments may beutilized and that process, electrical or mechanical changes may be madewithout departing from the scope of the present invention.

While described with reference to memory containers for fabrication of amemory array, embodiments of the invention may be used for fabricationof any other type of integrated circuit. For example, embodiments of theinvention may be used to fabricate other circuits, wherein the proximityof the structures are such that capillary forces may cause thestructures to lean and/or stick together. The terms wafer and substrateused in the following description include any base semiconductorstructure. Both are to be understood as including silicon-on-sapphire(SOS) technology, silicon-on-insulator (SOI) technology, thin filmtransistor (TFT) technology, doped and undoped semiconductors, epitaxiallayers of a silicon supported by a base semiconductor structure, as wellas other semiconductor structures well known to one skilled in the art.The following detailed description is, therefore, not to be taken in alimiting sense, and the scope of the present invention is defined onlyby the appended claims and their equivalents. It is noted that forpurposes of interpreting this disclosure and the claims that follow, thespacial reference terms “on”, “over”, “above”, “beneath” and the likeare utilized to describe relative orientations of various elements toone another. The terms are not utilized in an absolute and global senserelative to any external reference. Accordingly, a first materialrecited as being “beneath” a second material defines a reference of thetwo materials to one another, but does not mean that the first materialwould actually be “under” the second material relative to any referenceexternal of the two materials.

References in the specification to “one embodiment”, “an embodiment”,“an example embodiment”, etc., indicate that the embodiment describedmay includes a particular feature, structure, or characteristic, butevery embodiment may not necessarily include the particular feature,structure, or characteristic. Moreover, such phrases are not necessarilyreferring to the same embodiment. Further, when a particular feature,structure, or characteristic is described in connection with anembodiment, it is submitted that it is within the knowledge of oneskilled in the art to affect such feature, structure, or characteristicin connection with other embodiments whether or not explicitlydescribed.

FIG. 1 illustrates a system for semiconductor fabrication that includessurface tension control, according to one embodiment of the invention.In particular, FIG. 1 illustrates a system 100 that includes a vaporetch chamber 102 that may house a semiconductor substrate 104. Asfurther described in more detail below, the semiconductor substrate 104includes a layer/material that is to be vapor phase etched. In oneembodiment, the semiconductor substrate 104 includes a memory containerhaving a side wall that includes a double-sided capacitor. In anembodiment, the semiconductor substrate 104 includes an array of memorycells that are formed in a number of memory containers.

The vapor etch chamber 102 includes an inlet 107 and an outlet 108. Ahydrogen fluoride (HF) source 108 is coupled to input a hydrogenfluoride substance into a mix unit 112. In one embodiment, the hydrogenfluoride source 108 inputs an HF gas into the mix unit 112. In someembodiments, the system 100 may include an etch initiator source 110 (asshown) to input an etch initiator composition into the mix unit 112. Theetch initiator composition allows for a more uniform etching across thesemiconductor substrate 104 at about the time. In some embodiments, etchinitiation is not used. Etch initiator compositions may includedifferent forms of H₂O (e.g., an H₂O vapor), methanol, acetic acid,different types of ethers, acetone, carboxylic acid, etc.

Alternatively to the system 100, the etch initiator composition may beapplied outside of the mix unit 112. For example, the etch initiatorcomposition may be applied prior to the semiconductor substrate 104being housed in the vapor etch chamber 102. In addition or alternativeto the use of an etch initiator composition, ultraviolet light could beapplied to the surface of the semiconductor substrate 104 to allow forthe more uniform etching of the surface.

In an embodiment, the etch initiator source 110 inputs an etch initiatorcomposition into the mix unit 112. A surface tension lowering agentsource 106 is coupled to input a surface tension lowering agent into mixthe unit 112.

In an embodiment, the surface tension lowering agent includes analcohol. In one embodiment, the surface tension lowering agent includesan isopropyl alcohol. In an embodiment, the surface tension loweringagent includes a methanol. In one embodiment, the surface tensionlowering agent includes carboxylics. In an embodiment, the surfacetension lowering agent includes an acetic acid. In one embodiment, thesurface tension lowering agent includes trifluoroacetic acid. Moreover,the surface tension lowering agent may comprise a combination of thesedifferent embodiments. For example, the surface tension lowering agentmay include a combination of isopropyl alcohol and methanol.

The mix unit 112 may mix the HF gas, the etch initiator composition andthe surface tension lowering agent to form a mixed vapor. In oneembodiment, the mix unit 112 heats the HF, the etch initiatorcomposition and the surface tension lowering agent to generate a mixedvapor. In one embodiment, the surface tension lowering agent isapproximately 10% of the mixed vapor. In an embodiment, the surfacetension lowering agent is approximately 30% of the mixed vapor. However,embodiments of the invention are not limited to such percentages as thesurface tension lowering agent may be a greater or lesser percentage ofthe mixed vapor.

The mix unit 112 is coupled to a valve 114. The valve 114 is coupled tothe inlet 107. Accordingly, the valve 114 (when opened) releases themixed vapor into the vapor etch chamber 102. As described in more detailbelow, the mixed vapor etches at least one layer of the semiconductorsubstrate 102. Moreover, the surface tension lowering agent combineswith the product of the vapor etch operation to generate an absorbedlayer on the surface of the layer being etched.

Embodiments of the invention are not limited to the system 100illustrated in FIG. 1. For example, in an embodiment, the mix unit 112is not used. Accordingly, the HF source 108, the etch initiator source110 and the surface tension lowering agent source 106 are coupleddirectly to the valve 114. In another embodiment, the surface tensionlowering agent source 106 is coupled to directly input the surfacetension lowering agent directly into the vapor etch chamber 104, whilethe HF source 108 and the etch initiator source 110 are coupled to themix unit 112 to allow for premixing of the HF with the etch initiatorcomposition. In an embodiment, the system 100 may not include the etchinitiator source 110. Accordingly, the mixed vapor may be a combinationof an HF gas and a surface tension lowering agent in a vapor form.

A more detailed description of the vapor phase etching is now describedwith reference to FIGS. 2-4. FIG. 2 illustrates a semiconductorsubstrate, according to one embodiment of the invention. FIG. 2illustrates one embodiment of the semiconductor substrate 102. Thesemiconductor substrate 102 includes a first memory container 202 and asecond memory container 204 formed on a substrate 220. While the firstmemory container 202 and the second memory container 204 may have anumber of different aspect ratios, in one embodiment, the first memorycontainer 202 or the second memory container 204 has an aspect ratio of10:1. In an embodiment, the first memory container 202 or the secondmemory container 204 has an aspect ratio of 13:1.

The first memory container 202 and the second memory container 204 areformed in an insulator material 218 on the substrate 220 usingtechniques well known in the art, including masking, doping, etching,deposition, etc., or any combination thereof. Moreover, the first memorycontainer 202, the second memory 204 and the substrate 220 may be formedfrom a number of different materials known in the art.

In one embodiment, the insulator material 218 is an oxide. In anembodiment, the insulator material 218 is a doped oxide. In oneembodiment, the insulator material 218 includes silicon oxide. In anembodiment, the insulator material 218 includes silicon nitride. In oneembodiment, the insulator material 218 includes a silicon oxynitride.

The first memory container 202 includes a lower capacitor plate 216, andthe second memory container 204 includes a lower capacitor plate 210.The first memory container 202 includes a dielectric layer 214 formed onthe lower capacitor plate 216. The second memory container 204 includesa dielectric layer 208 formed on the lower capacitor plate 210. Thefirst memory container 202 includes an upper capacitor plate 212 formedon the dielectric layer 214. The second memory container 204 includes anupper capacitor plate 206 formed on the dielectric layer 208.

As shown, the first memory container 202 includes a side wall 250 havinga doubled-sided capacitor. In particular, the double-sided capacitorincludes the lower capacitor plate 216 surrounded on two sides by theupper capacitor plate 212. The second memory container 204 includes aside wall 252 having a double-sided capacitor. In particular, thedouble-sided capacitor includes the lower capacitor plate 210 surroundedon two sides by the upper capacitor plate 206.

FIG. 3 illustrates a fabrication of the semiconductor substrate of FIG.2 at a first stage, according to one embodiment of the invention. Asshown, the semiconductor substrate 102 is surrounded by a mixed vapor310. A vapor phase etch operation is performed to remove the insulatormaterial 218 using the mixed vapor 310. The mixed vapor may be comprisedof a number of different substances in combination with a surfacetension lowering agent (as described above in conjunction with FIG. 1above). As shown, an absorbed layer 302 is formed on the top of theinsulator material 218. The absorbed layer 302 includes the surfacetension lowering agent in combination of the results of the vapor phaseetch.

FIG. 4 illustrates a fabrication of the semiconductor substrate of FIG.2 at a second stage, according to one embodiment of the invention. Asshown, the semiconductor substrate 102 is surrounded by the mixed vapor310. The vapor phase etch operation continues to remove the insulatormaterial 210 using the mixed vapor 310. The absorbed layer 302 remainson the top of the insulator material 218.

Memory Devices

FIG. 5 is a simplified block diagram of a memory device, according toone embodiment of the invention. FIG. 5 illustrates a memory device 500includes an array of memory cells 502, an address decoder 504, a rowaccess circuitry 506, a column access circuitry 508, a control circuitry510, and an Input/Output (I/O) circuit 512. The memory device 500 isoperably coupled to an external processor 514, or memory controller (notshown) for memory accessing. The memory device 500 receives controlsignals from the processor 514, such as WE*, RAS* and CAS* signals. Thememory device 500 stores data which is accessed via I/O lines. It willbe appreciated by those skilled in the art that additional circuitry andcontrol signals can be provided, and that the memory device of FIG. 5has been simplified to help focus on embodiments of the invention. Atleast one of the memory cells, transistors, or associated circuitry hasan integrated circuit structure or element in accordance withembodiments of the invention. For example, the array of memory cells 502may be fabricated according to embodiments of the invention.

It will be understood that the above description of a memory device isintended to provide a general understanding of the memory and is not acomplete description of all the elements and features of a specific typeof memory, such as DRAM (Dynamic Random Access Memory). Further, theembodiments of the invention are equally applicable to any size and typeof memory circuit and are not intended to be limited to the DRAMdescribed above. Other alternative types of devices include SRAM (StaticRandom Access Memory) or Flash memories. Additionally, the DRAM could bea synchronous DRAM commonly referred to as SGRAM (Synchronous GraphicsRandom Access Memory), SDRAM (Synchronous Dynamic Random Access Memory),SDRAM II, and DDR SDRAM (Double Data Rate SDRAM), as well as Synchlinkor Rambus DRAMs and other emerging DRAM technologies.

Semiconductor Dies

FIG. 6 illustrates a semiconductor die, according to one embodiment ofthe invention. As shown, a semiconductor die 610 is produced from awafer 600. The semiconductor die 610 is an individual pattern, typicallyrectangular, on a substrate or wafer 600 that contains circuitry, orintegrated circuit devices, to perform a specific function. Thesemiconductor wafer 600 will typically contain a repeated pattern ofsuch semiconductor dies 610 containing the same functionality. Thesemiconductor die 610 is typically packaged in a protective casing (notshown) with leads extending therefrom (not shown) providing access tothe circuitry of the die for unilateral or bilateral communication andcontrol. The semiconductor die 610 may include an integrated circuitstructure or element in accordance with embodiments of the invention.

Circuit Modules

FIG. 7 illustrates a circuit module, according to one embodiment of theinvention. As shown in FIG. 7, two or more semiconductor dies 610 may becombined, with or without protective casing, into a circuit module 700to enhance or extend the functionality of an individual semiconductordie 610. The circuit module 700 may be a combination of semiconductordies 610 representing a variety of functions, or a combination ofsemiconductor dies 610 containing the same functionality. One or moresemiconductor dies 610 of circuit module 700 may contain at least oneintegrated circuit structure or element in accordance with embodimentsof the invention.

Some examples of a circuit module include memory modules, devicedrivers, power modules, communication modems, processor modules andapplication-specific modules, and may include multilayer, multichipmodules. The circuit module 700 may be a subcomponent of a variety ofelectronic systems, such as a clock, a television, a cell phone, apersonal computer, an automobile, an industrial control system, anaircraft and others. The circuit module 700 may have a variety of leads710 extending therefrom and coupled to the semiconductor dies 610providing unilateral or bilateral communication and control.

FIG. 8 illustrates a circuit module as a memory module, according to oneembodiment of the invention. A memory module 800 contains multiplememory devices 810 contained on a support 815 (the number generallydepending upon the desired bus width and the desire for parity). Thememory module 800 accepts a command signal from an external controller(not shown) on a command link 820 and provides for data input and dataoutput on data links 830. The command link 820 and data links 830 areconnected to leads 840 extending from the support 815. The leads 840 areshown for conceptual purposes and are not limited to the positions shownin FIG. 8. At least one of the memory devices 810 may contain anintegrated circuit structure or element in accordance with embodimentsof the invention.

Electronic Systems

FIG. 9 illustrates a block diagram of an electronic system, according toone embodiment of the invention. FIG. 9 shows one embodiment of anelectronic system 900 containing one or more circuit modules 700. Theelectronic system 900 generally contains a user interface 910. The userinterface 910 provides a user of the electronic system 900 with someform of control or observation of the results of the electronic system900. Some examples of the user interface 910 include the keyboard,pointing device, monitor or printer of a personal computer; the tuningdial, display or speakers of a radio; the ignition switch, gauges or gaspedal of an automobile; and the card reader, keypad, display or currencydispenser of an automated teller machine, or other human-machineinterfaces. The user interface 910 may further describe access portsprovided to electronic system 900. Access ports are used to connect anelectronic system to the more tangible user interface componentspreviously exemplified. One or more of the circuit modules 700 may be aprocessor providing some form of manipulation, control or direction ofinputs from or outputs to user interface 710, or of other informationeither preprogrammed into, or otherwise provided to, electronic system900. As will be apparent from the lists of examples previously given,the electronic system 900 will often be associated with certainmechanical components (not shown) in addition to the circuit modules 700and the user interface 910. It will be appreciated that the one or morecircuit modules 700 in the electronic system 900 can be replaced by asingle integrated circuit. Furthermore, the electronic system 900 may bea subcomponent of a larger electronic system. It will also beappreciated that at least one of the memory modules 700 may contain anintegrated circuit structure or element in accordance with embodimentsof the invention.

FIG. 10 illustrates a block diagram of an electronic system as a memorysystem, according to one embodiment of the invention. A memory system1000 contains one or more memory modules 800 and a memory controller1010. The memory modules 800 each contain one or more memory devices810. At least one of memory devices 810 may contain an integratedcircuit structure or element in accordance with embodiments of theinvention.

The memory controller 1010 provides and controls a bidirectionalinterface between the memory system 1000 and an external system bus1020. In an embodiment, the memory controller 1010 may contain anintegrated circuit structure or element in accordance with embodimentsof the invention. The memory system 1400 accepts a command signal fromthe external system bus 1020 and relays it to the one or more memorymodules 800 on a command link 830. The memory system 1000 provides fordata input and data output between the one or more memory modules 800and the external system bus 1020 on data links 1040.

FIG. 11 illustrates a block diagram of an electronic system as acomputer system, according to one embodiment of the invention. Acomputer system 1100 contains a processor 1110 and a memory system 1000housed in a computer unit 1105. The computer system 1100 is but oneexample of an electronic system containing another electronic system,i.e., memory system 1000, as a subcomponent. The computer system 1100optionally contains user interface components. Depicted in FIG. 11 are akeyboard 1120, a pointing device 1130, a monitor 1140, a printer 1150and a bulk storage device 1160. It will be appreciated that othercomponents are often associated with the computer system 1100 such asmodems, device driver cards, additional storage devices, etc. It willfurther be appreciated that the processor 1110 and the memory system1000 of computer system 1100 can be incorporated on a single integratedcircuit. Such single package processing units reduce the communicationtime between the processor and the memory circuit. It will beappreciated that at least one of the processor 1110 and the memorysystem 1000 may contain an integrated circuit structure or element inaccordance with embodiments of the invention. In an embodiment, theprinter 1150 or the bulk storage device 1160 may contain an integratedcircuit structure or element in accordance with embodiments of theinvention.

CONCLUSION

Thus, methods, apparatuses and systems for different embodiments forsemiconductor fabrication that includes surface tension control havebeen described. As illustrated, embodiments of the invention allow for afaster etch rate in comparison to conventional vapor phase etchoperations. For example, in one embodiment, a vapor phase etch operationis performed on a material adjacent to a memory container having a sidewall that includes a double-sided capacitor. As described above, such acontainer includes fine structures which are relatively close togetherthat need to remain isolated from each other. Accordingly,alterations/damages (such as bending) of this side wall needs to bereduced in order to preclude the structures therein from bending and/orcoming into contact with each other. As described above, embodiments ofthe invention introduce a surface tension lowering agent into the vapor,thereby lowering the surface tension that is resident on the surface ofthe layer being etched because of the absorbed layer. Therefore, theabsorbed layer on the surface of the layer being etched may be thicker(in comparison to typical approaches) while lowering the amount ofsurface tension that maybe present.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement which is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. Adaptations of theinvention will be apparent to those of ordinary skill in the art. Forexample, while described with reference to etching of layers that areadjacent to memory containers (having double-sided containers in theside wall), embodiments of the invention may be applicable to otherstructures wherein the amount of surface tension is to remain low topreclude damage to surrounding/adjacent structures. Accordingly, thisapplication is intended to cover any adaptations or variations of theinvention. It is manifestly intended that this invention be limited onlyby the following claims and equivalents thereof.

1. A system comprising: a processor to execute a number of instructions; and a memory to store at least a part of the number of instructions, the memory having a number of memory cells, wherein the number of memory cells includes a double-sided capacitor fabricated in a side wall of a memory container, the number of memory cells fabricated by: forming the memory container in an oxide; and vapor wet etching of a layer of the oxide with a vapor comprised of a hydrogen fluoride, an etch initiator composition and a surface tension lowering agent.
 2. The system of claim 1, wherein the surface tension lowering agent includes methanol.
 3. The system of claim 1, wherein the surface tension lowering agent includes an isopropyl alcohol.
 4. The system of claim 1, wherein the surface tension lowering agent includes carboxylic.
 5. The system of claim 1, wherein the oxide comprises a silicon oxide.
 6. An electronic system comprising: a processor; and a memory device comprising: an array of memory cells having a number of double-sided capacitors formed in side walls of structures on a substrate, wherein the array of memory cells are formed by: vapor phase etching of a layer of an insulator material formed adjacent to the side walls of the structures, wherein the vapor phase etching comprises: mixing a hydrogen fluoride and an isopropyl alcohol to form a mixed vapor; and inserting the mixed vapor into the chamber; and an address decoder to decode access requests from the processor to access data in the array of memory cells.
 7. The electronic system of claim 6, wherein the insulator material comprises a borophosphosilicate glass (BPSG) material.
 8. The electronic system of claim 6, wherein the insulator material comprises silicon nitride.
 9. The electronic system of claim 6, wherein the insulator material comprises a doped oxide.
 10. The electronic system of claim 6, wherein the insulator material comprises silicon oxide.
 11. An integrated circuit device comprising: a first memory container having a side wall that includes a double-sided capacitor; and a second memory container having a side wall that includes a double-sided capacitor, wherein the first memory container and the second memory container are formed by vapor phase etching, with a vapor, an oxide layer between the side wall of the first memory container and the side wall of the second memory container, wherein the vapor includes a surface tension lowering agent.
 12. The integrated circuit device of claim 11, wherein the surface tension lowering agent includes methanol.
 13. The integrated circuit device of claim 11, wherein the surface tension lowering agent includes an isopropyl alcohol.
 14. The integrated circuit device of claim 11, wherein the surface tension lowering agent includes carboxylic.
 15. The integrated circuit device of claim 11, wherein the oxide layer comprises a silicon dioxide.
 16. The integrated circuit device of claim 11, wherein the oxide layer comprises a doped oxide layer.
 17. A memory device comprising: an array of memory cells formed within a number of memory containers, a side wall of at least one of the number of memory containers having a double-sided capacitor, wherein the at least one of the number of memory containers is formed by vapor phase etching a layer adjacent to the side wall with a vapor that includes a surface tension lowering agent.
 18. The memory device of claim 17, wherein the surface tension lowering agent includes methanol.
 19. The memory device of claim 17, wherein the surface tension lowering agent includes an isopropyl alcohol.
 20. The memory device of claim 17, wherein the surface tension lowering agent includes carboxylic.
 21. The memory device of claim 17, wherein the surface tension lowering agent includes an acetic acid.
 22. The memory device of claim 17, wherein the layer includes silicon dioxide.
 23. The memory device of claim 17, wherein the layer includes a silicon nitride.
 24. An integrated circuit comprising: a substrate; and a memory container formed on the substrate by: forming the memory container in a borophosphosilicate glass (BPSG) material on the substrate, wherein a side wall of the memory container includes a double-sided capacitor; and removing at least a part of the BPSG material based on a vapor wet etch operation with a vapor comprised of a hydrogen fluoride gas and an alcohol.
 25. The integrated circuit of claim 24, wherein the alcohol includes methanol.
 26. The integrated circuit of claim 24, wherein the alcohol includes an isopropyl alcohol.
 27. An array of memory cells comprising: a substrate; and a structure having a side wall that includes a double-sided capacitor, wherein the structure is formed on the substrate by vapor phase etching a layer adjacent to the side wall with a vapor that includes methanol.
 28. The array of memory cells of claim 27, wherein the layer includes an insulator material.
 29. The array of memory cells of claim 27, wherein the layer includes a silicon dioxide.
 30. The array of memory cells of claim 27, wherein the layer includes a silicon nitride.
 31. A memory comprising: a substrate; and a number of memory containers having side walls that includes a double-sided capacitor, wherein the number of memory containers are formed on the substrate by etching an insulator layer adjacent to the side walls with a vapor that includes a hydrogen fluoride gas, an H₂O vapor and a surface tension lowering agent.
 32. The memory of claim 31, wherein the insulator layer includes an oxide.
 33. The memory of claim 31, wherein the insulator layer includes a doped oxide.
 34. The memory of claim 31, wherein the surface tension lowering agent
 35. The memory of claim 31, wherein the surface tension lowering agent includes an isopropyl alcohol.
 36. The memory of claim 31, wherein the surface tension lowering agent includes carboxylic.
 37. The memory of claim 31, wherein the surface tension lowering agent includes a trifluoroacetic acid. 